Cache line width

[mcostalba]

Where can I find the width of the cache line for the various processors?

I have found only the specs for the K8 family here (64 bytes of cache line):

http://en.wikipedia.org/wiki/CPU_cache

Could someone please give me some link to this info ?

Thanks
Marco

[Aleks Peshkov]

All modern x86 CPUs of all vendors have 64 bytes per line. http://www.agner.org/optimize/#manuals

[mcostalba]

All modern x86 CPUs of all vendors have 64 bytes per line. http://www.agner.org/optimize/#manuals

Thanks for the link, very appreciated.

But at least Intel® Xeon® cache line seems to be 128 bytes

"For instance, cache lines for Intel® Xeon® processor are laid out in 128 byte lines that always start at an address that is a multiple of 0x80"

The above is extracted from:
http://software.intel.com/en-us/articles/false-sharing/

[Gian-Carlo Pascutto]

P4 (Xeon) had 128 byte cacheline size.

[bob]

P4 (Xeon) had 128 byte cacheline size.

and 32 L1 cache line size if memory serves... There were a few editions of the pentium-pro architecture that had 32byte l1, and then 64/128 L2.

[mcostalba]

P4 (Xeon) had 128 byte cacheline size.

and 32 L1 cache line size if memory serves... There were a few editions of the pentium-pro architecture that had 32byte l1, and then 64/128 L2.

Perhaps CPU with very long cache lines are mainly intended for single core systems, where big cache lines are a good thing and don't have issues due to SMP.

[bob]

P4 (Xeon) had 128 byte cacheline size.

and 32 L1 cache line size if memory serves... There were a few editions of the pentium-pro architecture that had 32byte l1, and then 64/128 L2.

Perhaps CPU with very long cache lines are mainly intended for single core systems, where big cache lines are a good thing and don't have issues due to SMP.

I think it came along as a support for RAMBUS, which died a well-deserved death.

[mathmoi]

Hi Marco,

On Linux you can check in /proc/cpuinfo. In this questions on stackoverflow.com I asked this very question and got some answers : http://stackoverflow.com/questions/1502 ... -size-in-c

[wgarvin]

P4 (Xeon) had 128 byte cacheline size.

and 32 L1 cache line size if memory serves... There were a few editions of the pentium-pro architecture that had 32byte l1, and then 64/128 L2.

Perhaps CPU with very long cache lines are mainly intended for single core systems, where big cache lines are a good thing and don't have issues due to SMP.

The 3 PowerPC cores of the Xbox360 and the PPU of the PS3's Cell processor both use 128-byte cachelines throughout (L1 and L2).

[mcostalba]

Hi Marco,

On Linux you can check in /proc/cpuinfo. In this questions on stackoverflow.com I asked this very question and got some answers : http://stackoverflow.com/questions/1502 ... -size-in-c

Thanks for the link !

I didn't know that site, it is an interesting one.