Dann Corbit wrote:It is plain that you know more about FPGAs than I do. I am somewhat surprised that they do not obey Moore's law.
Moore's law is about transistor count, not clockspeed. Clockspeed creeps up slowly on FPGAs for reasons mentioned above, but the amount of logic you can get at a certain pricepoint increased much more.
You could probably fit a bunch of DB/Hydra style "cores" into a single "cheap" FPGA now, but then you'd still be stuck with the problem of the parallelization loss.
Is it possible to use the VHDL for an FPGA to create an ordinary CMOS device (like a general purpose CPU)?
Sure (MicroBlaze, Nios, Cortex-M0, etc). This will get you a slow CPU at a relatively large logic cost. There are some uses, but performance is not one of them.
Donninger published enough about Hydra that you can get some rough estimates. They had a 50Mhz (Virtex2) running at 9 cycles per node occupying about 18000 LE, meaning a chip did about 5.5Mnps.
You can then make some assumptions like that a Virtex-6 would attain 100Mhz for the same design, and maybe Spartan-6 50Mhz (Those are of course rough guesses.) Then go hunt on Xilinx's site and AvNet what size FPGA is most cost efficient for fitting as much of those cores on it as possible (make sure to take a conservative estimate because you won't be able to "fill" the FPGA over say 75% without compromising the clockspeed).
Now, divide everything by the ELO loss caused by loss of:
- hashtables last few ply
- no killers, history or SEE in move ordering
And compare to what cluster you can build using commodity hardware. I think it's already clear what side of this comparison I'm on.