bob wrote:It happens whenever an interrupt is being processed as the most common example, where it is automatic in fact.
Well, that depends on the hardware.
With Intel CPUs and the like, there are explicit instructions
EI and
DI for enabling/disabling interrupts. There's an interrupt flip flop that comes up reset at power up and stays that way until set by an
EI then later reset with a
DI.
I vaguely recall some boot code for various CPUs where the very first instruction executed was a DI or the equivalent, just to make sure that there would be no door knockers before the CPU could put its mind together.
Now a CPU, or an attached programmable interrupt controller chip, can have an interrupt mask which allows only certain interrupts to be acknowledged; the CPU can also have an interrupt level register which permits interrupts based on priority (e.g., Motorola CPUs). Either way, interrupts are not automatically disabled when one occurs, but one interrupt can suspend all others of less priority.
And if a CPU has an NMI (non maskable interrupt) capability, nothing can block that. On the early Macintosh models, an NMI could be manually generated by pressing the hidden Programmer's Switch; this would tickle the CPU's NMI pin to unfreeze a locked-up Mac and activate the internal debugger. I used this many times during the development of
Spector. Next to the NMI button was a second secret button which would send a reset to the CPU's RESET pin, and I used that a lot as well.
Now I know that you know all of this, but perhaps there are some readers here who are less familiar with this particular low level technology.
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It was long ago and far away, but I can still recall an undergraduate programming class where there were only two assignments:
1) Write a microkernel which serviced interrupts with the servicing done with interrupts disabled;
2) Write a microkernel which NEVER disabled interrupts.
Many students had quite a bit of difficulty with the latter of the two.