TalkChess.com

To get back on topic: It still bothers me that at split points there would be multiple threads each generatinfg moves for the same position. So I wonder if there would be some gain in having only one thread, the one that 'owns' the node and has opened the hash entry for it, to generate moves, and p...

The math looks tough to me. 16K lines mapping into a set that only holds 16 line, is a 1024 to 1 mapping. Not really. Because 1024 is a large number, randomly assigning the pages becomes the same as randomly deciding per page if it is used or not, with a certain probability. This leads to Poisson s...

You can easily do that. But the cost is prohibitive, in that the program will play so incredibly weakly because of the internet latency. Currently you do a probe and get an answer back in a few milliseconds. On the internet, multiply that by 100 or 1000, and it would absolutely kill the search spee...

In this game http://www.chessgames.com/perl/chessgame?gid=1441216 there is mention of a sideline analyzed by GM Golubov. The end of the line is this position: [D] 5k1r/r3b2p/p3Qp2/qp1p4/8/2R5/1PP2PPP/4R1K1 w - - here it is said h4 is winning but computers take "several minutes" to see it. I tried A...

l have a good position structure well suited to SMP, I think. I am still not sure how best to handle move history for rep detection across multiple processors. but it seems to be going well. Mark, WOW - big step! Here's what I'd do (actually have done - I seem to have rewrite-titis) when re-writing...

Another way to look at it is this: Suppose the processing of each node causes N cache misses (hash probe included), that are randomly distributed over L2. Then in a 4MB cache, with 64K lines, you need a tree of 64K/N nodes before (on the average) a probed entry is flushed from the cache before the ...

The point is that when you allocate x cache-ways worth of memory as randomly scattered pages, The probability for N items to map into the same cache line has a Poissson distribution P(N) = x^N/N! exp(-x). For x=1 (e.g. 1MB in a 4-way 4MB cache) the probability that more than 4 items map into a line...

Well, like I said, I am doing this so far only for L1, as all frequently used data except the main hash easily fits there (if it is not a P-IV). L1 is indexed by the _logical_ address, not the _physical_ address (although it is physically tagged). Although the memory management could indeed scatter...

I have one. It is nowhere near SCSI. And I do mean _nowhere_ near...

I do the same since I extend a check when I give it, rather than when I escape it. I can't get to the q-search in check, although once in the q-search it can certainly happen when a capture gives check.