How fast was the Cray?

[elpapa]

I found this chart comparing MFLOPS:

http://pages.experts-exchange.com/proce ... -compared/

According to this, the original iPhone was slightly faster than a Cray-1, and an iPhone 6 is about 15 times faster than the first iPhone. The Tianhe-2 super-computer is almost 100 million times as fast as the Cray-1, provided that I got all the zeroes right.

[M ANSARI]

I wonder what ELO rating the engine that won would have today. Would it be able to take on SF on an iwatch?

[Leo]

I like that picture. I am sure "the boys" have a lot of nostalgia with that picture.

[bob]

...
The Cray had wonderful memory bandwidth, and could stream 64-bit data from and to memory at the clock speed of the CPU. Modern CPUs can only do that from their (tiny) level 1 cache.

That was a reason for the high price of this machines : memory !

Waiting for MRAM ( https://en.wikipedia.org/wiki/Magnetore ... ess_memory ) on PCs : 2 ns access time !

Actually Cray eventually went to normal DRAM. The difference was (a) word length, and that EVERY part of the system was pipelined.

IE if you wanted to compute this:

For (i=0;i<1000000;i++)

x = a*b+c

You could produce one x per clock cycle, which included reading all the crap from memory and writing x back. Can't do that even today on the PC. It gave an effective memory access/cycle time of whatever the CPU ran at with ZERO waiting after start-up.

The other claim to fame was the fully connected cross-bar to connect memory banks to CPUs to minimize/eliminate bank conflicts for vector operations... And this machine was fully SMP, no NUMA to be found.

[Laskos]

I wonder what ELO rating the engine that won would have today. Would it be able to take on SF on an iwatch?

Come on, iWatch CPU is the level of that of a weak modern smartphone, in other words, stronger than Cray-1. Software wise, at least 500 ELO points difference.

[reflectionofpower]

The one I calculated on (Cray Y-MP) was double that (167 MHz).

IIRC Cray Y-MP appeared in 1988 or so. The OP picture is from 1984, and I assumed they used Cray-1M or similar with 80MHz.

That photo was taken at the end of the 1983 WCCC event in NYC. We were, as I said, running on the Cray XMP prototype which was an 8ns machine with two cpus. In 1984 we won the ACM event running on the next version of this, the XMP-4 with 4 cpus. The YMP was the machine we used to win the 1986 WCCC event in Cologne, it had 8 cpus and a 6ns clock speed.

BTW THESE numbers I recall quite well. For obvious reasons.

heehee

[Vinvin]

...
The Cray had wonderful memory bandwidth, and could stream 64-bit data from and to memory at the clock speed of the CPU. Modern CPUs can only do that from their (tiny) level 1 cache.

That was a reason for the high price of this machines : memory !

Waiting for MRAM ( https://en.wikipedia.org/wiki/Magnetore ... ess_memory ) on PCs : 2 ns access time !

Actually Cray eventually went to normal DRAM. The difference was (a) word length, and that EVERY part of the system was pipelined.

IE if you wanted to compute this:

For (i=0;i<1000000;i++)

x = a*b+c

You could produce one x per clock cycle, which included reading all the crap from memory and writing x back. Can't do that even today on the PC. It gave an effective memory access/cycle time of whatever the CPU ran at with ZERO waiting after start-up.

The other claim to fame was the fully connected cross-bar to connect memory banks to CPUs to minimize/eliminate bank conflicts for vector operations... And this machine was fully SMP, no NUMA to be found.

Here https://en.wikipedia.org/wiki/Cray_Y-MP , I read

Main memory comprised 128, 256 or 512 MB of SRAM.
...
The Y-MP M90 was a large-memory variant of the Y-MP Model E introduced in 1992. This replaced the SRAM of the Y-MP with up to 32 GB of slower, but physically smaller DRAM devices.

SRAM is way more expensive than DRAM.

[mar]

http://pages.experts-exchange.com/proce ... -compared/

OT: That chart has some flaws, 2 MFLOPS on Atari 2600?! Give me a break
1MHz 6502 (no FPU), 2 cycles minimum per instruction...

[elpapa]

http://pages.experts-exchange.com/proce ... -compared/

OT: That chart has some flaws, 2 MFLOPS on Atari 2600?! Give me a break
1MHz 6502 (no FPU), 2 cycles minimum per instruction...

Yes, that is obviously way off. And no need to use math either, you just have to look at it.

[Vinvin]

http://pages.experts-exchange.com/proce ... -compared/

OT: That chart has some flaws, 2 MFLOPS on Atari 2600?! Give me a break
1MHz 6502 (no FPU), 2 cycles minimum per instruction...

Yes, that is obviously way off. And no need to use math either, you just have to look at it.

I second that, the 8087 was way faster than 8086 in math and the 8086 was way faster than 6502 in math.
"The 8087 could perform about 50,000 FLOPS" from https://en.wikipedia.org/wiki/Intel_8087
I estimate the 6502 did less than 0.001 MFLOPS.