Any good for chess?

[Werewolf]

https://www.anandtech.com/show/12773/in ... to-vendors

Could this be used to accelerate engines?

[Eelco de Groot]

https://www.anandtech.com/show/12773/in ... to-vendors

Could this be used to accelerate engines?

I know nothing about FPGAs but if I remember correctly that is hardware suited for Deep Blue kind of programs, and Hydra. You could program an evaluation function in hardware. But almost nobody would have this chip to run it... It costs an arm and a leg Maybe it is meant for military purposes? A Xeon with programmable hardware is not something you build into a washing machine or a vending machine. It is not compatible with learning programs that are so miraculously suited to graphical floating point hardware and now TPUs.

I suspect we have seen the last of Deep Blue kind of programs, at least competing for the ICGA title or anything like that. Unless the chip can be used as a Neural Network (in hardware) which does not seem impossible. Not learning, but fast.

[Dann Corbit]

The problem with the FPGA approach is that it is very expensive and once completed it is cast in stone.
In other words, you spend a big pile of money, and you do get a super-fast whatever you are building.
But next year it runs at the same speed. And next year the algorithms do not (and can not) improve.
Meanwhile everyone else's hardware is twice as fast. And everyone else's software is twice as fast.
And next year it happens again. And the year after that and the year after that.
So you spent a zillion dollars for what is eventually a boat anchor.

Like the Hitech approach or the Deep Blue approach or the Hydra approach... Current software on TCEC hardware would give those things a big time spanking.

On the other hand, if you want to win today and you have very deep pockets, then it will work.

[Milos]

https://www.anandtech.com/show/12773/in ... to-vendors

Could this be used to accelerate engines?

Ofc it could. Problem is, chess programmers actually capable of programming something even marginally efficient in FPGA beyond useless C to VHDL/Verilog translation are measured in low single digit numbers and those who could actually do it would never do it for free, because it requires a lot of time and as Dann pointed out is extremely hard to be kept up to date .

[Milos]

The problem with the FPGA approach is that it is very expensive and once completed it is cast in stone.
In other words, you spend a big pile of money, and you do get a super-fast whatever you are building.
But next year it runs at the same speed. And next year the algorithms do not (and can not) improve.
Meanwhile everyone else's hardware is twice as fast. And everyone else's software is twice as fast.
And next year it happens again. And the year after that and the year after that.
So you spent a zillion dollars for what is eventually a boat anchor.

Your knowledge is seems to be a bit outdated .
Speed up in recent Xilinx FPGA generations (for lets say past 5 years) is much higher than in Intel CPUs.
So if you had a fixed eval function in FPGA, just compiling it for newer generation boards would give you more speed up than running same software eval function on newer generation CPUs.
Moreover growth in terms of resources on FPGA is faster than in terms of number of cores on Intel CPUs.

[Werewolf]

The problem with the FPGA approach is that it is very expensive and once completed it is cast in stone.

I thought one of the big advantages of FPGA over ASIC was that it wasn't cast in stone and could be reprogrammed. I seem to remember talking to Chrilly D about this and he described FPGA as a half way house between software and ASIC with speed gains inbetween as well.

[Dann Corbit]

Yes, that is right. You can erase it and put new code on it.
It won't run any faster as far as MHz, but you could put new algorithms on it.
So it is kind of a half way solution for that part.

I have never programmed an FPGA, so I am not an expert on them, but I guess that they use VHDL like the ASICs do.

[hgm]

Of course it depends a lot on what task exactly you would be accelerating with the FPGA. If it would be a full hardware implementation of a specific evaluation function it would be very inflexible. If you would make something to fastly run neural-network inference, by having thousands of 8-bit x 8-bit multipliers that calculate one or more convolutional filters in parallel, but remain relying on software (possibly stored in an on-chip sequencer), you could keep using the same hardware even when completely changing the NN architecture. Because the architecture is define by the programming, an the hardware just performs the elementary steps, each at lightning speed.

Basically it amounts to designing and building your own TPU. Which sounds like a quite interesting project in itself. I have been designing digital hardware since the late seventies, an it was a very satisfying hobby.

[Joost Buijs]

Altera/Intel Stratix 10 is currently one of the fastest FPGA's available, unfortunately you got to have very deep pockets to afford a development kit for it.

https://www.altera.com/products/boards_ ... -fpga.html

These things always have my interest, several years ago I used to play at work with predecessors of this device.

[Milos]

Altera/Intel Stratix 10 is currently one of the fastest FPGA's available, unfortunately you got to have very deep pockets to afford a development kit for it.

https://www.altera.com/products/boards_ ... -fpga.html

These things always have my interest, several years ago I used to play at work with predecessors of this device.

I am not sure even about the speed. I regularly run some Ultrascale+ family IP blocks and simple custom logic at 600+ MHz.
Also price-wise they are awful especially now since Intel bought them.
For the same number of LUTs and functionality you can get Ultrascale+ FPGA kit for like 3k$ that Intel charges 8k$.