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Xilinx UltraScale Questions
Posted: Thu Apr 18, 2019 6:44 pm
by Leo
Can these be used for chess engines? How much are they? Will they hook up with a HEDT? Thanks.
Re: Xilinx UltraScale Questions
Posted: Thu Apr 18, 2019 7:09 pm
by Milos
Leo wrote: ↑Thu Apr 18, 2019 6:44 pm
Can these be used for chess engines? How much are they? Will they hook up with a HEDT? Thanks.
Sure they can. It doesn't matter how much FPGA's are. It would cost significantly more to make a functional chess engine on one. Coz:
1) Very few ppl (less than a handful) can actually do it
2) It would take a large effort to do it
In other words it's not enthusiasts kind of effort. It's an effort for the well paid experts.
Re: Xilinx UltraScale Questions
Posted: Thu Apr 18, 2019 7:43 pm
by Leo
Thanks. I will no longer consider it relevant for chess.
Re: Xilinx UltraScale Questions
Posted: Thu Apr 18, 2019 8:25 pm
by hgm
It would be interesting to know how powerful a TPU one could make from these things, for simulating neural nets.
Re: Xilinx UltraScale Questions
Posted: Fri Apr 19, 2019 1:31 am
by Milos
hgm wrote: ↑Thu Apr 18, 2019 8:25 pm
It would be interesting to know how powerful a TPU one could make from these things, for simulating neural nets.
Not enough. I did an analysis at one point after the first gen TPU appeared and you could get maybe half TOPS of the first get TPU (like around 50) with the largest Virtex Ultrascale+ chip at that time (I think it was 9P with 2.5 million LUTs and like 7k DSPs).
If you want anything competitive these days in CMOS you need at least 10nm ASIC.
There are however, other ways beyond CMOS
.