Actually the Epyc 7262 has two working cores per CCD ( 1 working core per CCX +3 defective cores), so 6 defective cores per CCD time 4 CCD's per chip. All else in your post seems correct.dragontamer5788 wrote: ↑Fri Nov 08, 2019 12:03 amThey do by design. But when a core is defective, AMD will sell it as a 6-core, 4-core, or even 1-core chiplet.
For example, the 8-core EPYC 7262 has 8x chiplets, 8x cores (1-working core + 7-defective cores per chiplet) and 128MB of L3 cache. https://www.servethehome.com/amd-epyc-7 ... ge-caches/
The huge aggregate L3 cache is useful in some workloads, and very cheap because 56 of the 64 cores are broken.