Dual EPYC

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Dann Corbit
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Joined: Wed Mar 08, 2006 8:57 pm
Location: Redmond, WA USA

Re: Dual EPYC

Post by Dann Corbit »

TMSC and AMD have hit the mark every other cycle in the past (three times now) so they have a good history.
It is bad business to set up expectations and then fail to fulfull them, so I don't think they will intentionally promulgate bad information.

And if they are late, then they are late. Intel did have that happen to them with their 10nm stuff and had to do delay after delay, and it could happen to AMD too. That is another reason to get current stuff when you can.

I bought a 3970x and I am just thrilled with it. I get more output with less electricity by far compared to all my other systems.
The wisdom of waiting is that you get exponentially more powerful hardware at the same price. The wisdom of buying now is that you have full advantage of the current best and we don't know what the future will bring.

I plan to buy the 5nm stuff too, and hopefully in 2021, but if not then 2022 and if not then 2023.
Taking ideas is not a vice, it is a virtue. We have another word for this. It is called learning.
But sharing ideas is an even greater virtue. We have another word for this. It is called teaching.
smatovic
Posts: 2645
Joined: Wed Mar 10, 2010 10:18 pm
Location: Hamburg, Germany
Full name: Srdja Matovic

Re: Dual EPYC

Post by smatovic »

Milos wrote: Tue Apr 28, 2020 10:03 pm
smatovic wrote: Tue Apr 28, 2020 7:55 pm Hehe, our insider speaks, it seems I am more a pessimist...
N5 Status
TSMC’s 5-nanometer node entered risk production early last year. C.C. Wei confirmed that N5 is now in volume production with good yield. We have recently covered TSMC 5-nanometer node disclose from a number of conferences. The node will deliver around 1.8x improvement in density along with 15% higher speed at iso-power or, alternatively, 30% lower power at the same speed. N5, like N7, is expected to remain a long-lasting node. “We expect a very fast and smooth ramp of N5 in the second half of this year driven by both mobile and HPC applications,” C.C. Wei added. TSMC estimates that N5 will contribute about 10% of wafer revenue in 2020. TSMC is observing a higher number of tape-outs compared to N7 at the same period of time during their ramp.
https://fuse.wikichip.org/news/3453/tsm ... illimeter/

But for sure your crystal ball has more to offer...
Well done, you quote TSMC PR guy advertising their product. And you can laugh as much as you like, but for your info, as someone who is actually doing ASIC design in 5nm as we speak, I know pretty well the situation.
And you, I bet you didn't even read a single paper related to 5nm technology, let alone ever seen a design manual or rule book.
Hmm, Dr. C.C. Wei is the CEO of TSMC, if this counts for you as PR guy, then
hey, okay...you are here the hardware guy, not me, I just read silly articles,
not the papers that matters ;)

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Srdja
Milos
Posts: 4190
Joined: Wed Nov 25, 2009 1:47 am

Re: Dual EPYC

Post by Milos »

smatovic wrote: Wed Apr 29, 2020 8:08 am Hmm, Dr. C.C. Wei is the CEO of TSMC, if this counts for you as PR guy, then
hey, okay...you are here the hardware guy, not me, I just read silly articles,
not the papers that matters ;)
Again you are incapable of differentiating between PR and actual factual data.
If data he presented was actual and not PR he would have given some yield figures. He didn't give them because they are awful.
Yes they get 80% yield out of 15mm2 die. But once you start increasing die size yield drops exponentially. With ~100mm2 it's not even 30%. Now go and figure out what is the typical die size of Zen3 CPUs.
Sure you can make production with 30% yield but you are not gonna get many customers coz the fabrication will be 5x more expensive for the customer.
Ofc they can make CPUs for iPhones but that's a totally different ballgame.
My advice to you is to first educate yourself on the basics which you clearly don't know.
smatovic
Posts: 2645
Joined: Wed Mar 10, 2010 10:18 pm
Location: Hamburg, Germany
Full name: Srdja Matovic

Re: Dual EPYC

Post by smatovic »

Milos wrote: Wed Apr 29, 2020 8:49 am
smatovic wrote: Wed Apr 29, 2020 8:08 am Hmm, Dr. C.C. Wei is the CEO of TSMC, if this counts for you as PR guy, then
hey, okay...you are here the hardware guy, not me, I just read silly articles,
not the papers that matters ;)
Again you are incapable of differentiating between PR and actual factual data.
If data he presented was actual and not PR he would have given some yield figures. He didn't give them because they are awful.
Yes they get 80% yield out of 15mm2 die. But once you start increasing die size yield drops exponentially. With ~100mm2 it's not even 30%. Now go and figure out what is the typical die size of Zen3 CPUs.
Sure you can make production with 30% yield but you are not gonna get many customers coz the fabrication will be 5x more expensive for the customer.
Ofc they can make CPUs for iPhones but that's a totally different ballgame.
My advice to you is to first educate yourself on the basics which you clearly don't know.
Hehe, like I said, you are here the insider with the numbers....

so what does your crystal ball say for AMD switching to 5nm in 2021/2022?

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Srdja