New AMD Zen 3 and Ryzen processors

[mvanthoor]

Don't count on it that Zen 3 will have a better implementation of PEXT/PDEP, besides this omission the Zen 2 is not a bad CPU at all.
Intels x299 platform is not bad either, it still has pcie 3.0 instead of 4.0, is this really a problem?
Pretty soon new HEDT platforms will all have DDR5 support, does this mean that DDR4 is bad?

Of course the 3970x isn't a 'bad' CPU, but when I want to go and implement PEXT bitboards, I can't test the improvement on that CPU because it'll actually become slower. The x299 platform is also not 'bad', but it's also almost 4 years old. I don't intend to buy a 4 year old platform at this time; I'm not a big business that plans to have a platform in operation for 10+ years before even starting to look at a replacement.

[syzygy]

So... any word on the implementation of BMI2, PEXT and PDEP?

If it's still as bad as Ryzen 2, these CPU's are out of the question for me. (Also, they are built on an old platform when using AM4; just like Intel 10-xx CPU's built on the X299 platform from 2017.)

I was doing some thinking on why AMD has not done PEXT very efficiently and it is probably that INTEL has their implementation patented. I don't know if that is the case or not but if it is then someone show AMD this.
http://www.open-aurec.com/wbforum/viewt ... ain#p28725
It might give AMD more leeway in how they can implement their PEXT instruction as the inventor of the instruction, myself, gives AMD permission to implement their version based solely off of my description of the instruction from 2006.

That's a pretty nice post indeed. Looks like you came up with one instruction that combines the functionality of pext and pdep.

There are patents on pext but I kind of doubt that they are the reason why AMD chose to implement these instructions in inefficient microcode. In the end they do implement the instruction, so they would probably still be infringing the patent.

Still earlier prior art:
https://patentimages.storage.googleapis ... 5945A1.pdf

[Joost Buijs]

Don't count on it that Zen 3 will have a better implementation of PEXT/PDEP, besides this omission the Zen 2 is not a bad CPU at all.
Intels x299 platform is not bad either, it still has pcie 3.0 instead of 4.0, is this really a problem?
Pretty soon new HEDT platforms will all have DDR5 support, does this mean that DDR4 is bad?

Of course the 3970x isn't a 'bad' CPU, but when I want to go and implement PEXT bitboards, I can't test the improvement on that CPU because it'll actually become slower. The x299 platform is also not 'bad', but it's also almost 4 years old. I don't intend to buy a 4 year old platform at this time; I'm not a big business that plans to have a platform in operation for 10+ years before even starting to look at a replacement.

The problem is that it will take at least another year before Intel comes with something new, probably even longer (2022). This is why I decided to replace my two old machines (i7-5960X and i7-6950X) with something new. I just didn't want to wait any longer.

If there really is something (much) better within two or three years or so, I will switch again.

[Mike Sherwin]

So... any word on the implementation of BMI2, PEXT and PDEP?

If it's still as bad as Ryzen 2, these CPU's are out of the question for me. (Also, they are built on an old platform when using AM4; just like Intel 10-xx CPU's built on the X299 platform from 2017.)

I was doing some thinking on why AMD has not done PEXT very efficiently and it is probably that INTEL has their implementation patented. I don't know if that is the case or not but if it is then someone show AMD this.
http://www.open-aurec.com/wbforum/viewt ... ain#p28725
It might give AMD more leeway in how they can implement their PEXT instruction as the inventor of the instruction, myself, gives AMD permission to implement their version based solely off of my description of the instruction from 2006.

That's a pretty nice post indeed. Looks like you came up with one instruction that combines the functionality of pext and pdep.

There are patents on pext but I kind of doubt that they are the reason why AMD chose to implement these instructions in inefficient microcode. In the end they do implement the instruction, so they would probably still be infringing the patent.

Still earlier prior art:
https://patentimages.storage.googleapis ... 5945A1.pdf

The difference between my suggestion and that earlier patent is that my idea also includes a destination mask. Anyway, I'm going back to work on my chess engine now.

[mvanthoor]

The problem is that it will take at least another year before Intel comes with something new, probably even longer (2022). This is why I decided to replace my two old machines (i7-5960X and i7-6950X) with something new. I just didn't want to wait any longer.

If there really is something (much) better within two or three years or so, I will switch again.

Understandable. In my case, my old i7-6700K + GTX 1070 with 32 GB RAM, 512 GB NMVE SSD and a 2 TB HDD works fine. If I hadn't gotten into chess programming, I wouldn't have considered replacing this machine. Maybe I'll even keep the GTX 1070 in a new computer, because I only play old games. The Witcher 3 is still (by far) the most demanding game I run. I had my previous computer for 7 years.

I still have my old Dell E6500 laptop (P8600 Core2 Duo), now 12 years old, lying around. It was upgraded from Vista to 7 to Windows 10, and it still works for some office tasks... even though opening a few websites nowadays almost buries it.

[Milos]

So... any word on the implementation of BMI2, PEXT and PDEP?

If it's still as bad as Ryzen 2, these CPU's are out of the question for me. (Also, they are built on an old platform when using AM4; just like Intel 10-xx CPU's built on the X299 platform from 2017.)

In the light of NNUE who needs BMI2, PEXT or PDEP and what for???
For computer chess they are relict of the past. What we really need is fast AVX512 implementation and even better fast new SIMD instructions like 1024 bits vector multiplication for bfloat16 as well as for int8.

[Ozymandias]

In the light of NNUE who needs BMI2, PEXT or PDEP and what for???

In the posts above, some programmers have answered. They need them to better carry on with their profession.

[Milos]

In the light of NNUE who needs BMI2, PEXT or PDEP and what for???

In the posts above, some programmers have answered. They need them to better carry on with their profession.

Lol, and which profession is that exactly?

[Joost Buijs]

So... any word on the implementation of BMI2, PEXT and PDEP?

If it's still as bad as Ryzen 2, these CPU's are out of the question for me. (Also, they are built on an old platform when using AM4; just like Intel 10-xx CPU's built on the X299 platform from 2017.)

In the light of NNUE who needs BMI2, PEXT or PDEP and what for???
For computer chess they are relict of the past. What we really need is fast AVX512 implementation and even better fast new SIMD instructions like 1024 bits vector multiplication for bfloat16 as well as for int8.

Computer chess is not the only thing in this world. NNUE is a bit overhyped too, it's not the be all and end all. In some time there will be something completely different, that is how it goes and how it always has been.

[Milos]

So... any word on the implementation of BMI2, PEXT and PDEP?

If it's still as bad as Ryzen 2, these CPU's are out of the question for me. (Also, they are built on an old platform when using AM4; just like Intel 10-xx CPU's built on the X299 platform from 2017.)

In the light of NNUE who needs BMI2, PEXT or PDEP and what for???
For computer chess they are relict of the past. What we really need is fast AVX512 implementation and even better fast new SIMD instructions like 1024 bits vector multiplication for bfloat16 as well as for int8.

Computer chess is not the only thing in this world. NNUE is a bit overhyped too, it's not the be all and end all. In some time there will be something completely different, that is how it goes and how it always has been.

There is hardly any application that can noticably benefit from PEXT type of instructions. If this was a vector instruction to extract ints or floats from a vector like what CUDA supports on GPU hardware I would understand. But this kind of bit manipulation is a nishe application that has very little relevance except for computer chess programmer geeks.