New Mainframe Tech -- Any Potentials for Chess?

[mhull]

IBM z6 Highlights
New high-frequency z/Architecture microprocessor core
>4 GHz operation in system

4 cores per die
• Each with 3MB private 2nd-level cache

Accelerator engines
• Data compression
• Cryptographic functions
• Decimal floating point

Integrated SMP communications
• Switch connects cores to SMP Hub chip
• Shared cache and SMP fabric
• Memory bus controller
• I/O bus controller
• EI3 technology up to 3 GHz bus speeds

System interfaces
• 2 x 48 GB/s SMP Hub
• 4 x 13 GB/s Memory
• 2 x 17 GB/s I/O

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