AMD's X3D - HBM on CPU - memory wall

[smatovic]

Seems AMD plans to put HBM on CPUs, increases bandwidth 10 fold they say.

https://www.anandtech.com/show/15590/am ... 25d-and-3d

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Srdja

[Leo]

Seems AMD plans to put HBM on CPUs, increases bandwidth 10 fold they say.

https://www.anandtech.com/show/15590/am ... 25d-and-3d

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Srdja

Good news.

[smatovic]

Followup...

Fujitsu put 32 GB HBM on their ARM based A64FX processor with 1 TB/s

https://en.wikipedia.org/wiki/Fujitsu_A64FX

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Srdja

[Dann Corbit]

Seems AMD plans to put HBM on CPUs, increases bandwidth 10 fold they say.

https://www.anandtech.com/show/15590/am ... 25d-and-3d

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Srdja

What wonderful news. And since CPUs and GPUs both can talk to the same greased-lightning fast memory, think of the stories we could tell.

[smatovic]

I like the new POWER10 design...

https://en.wikipedia.org/wiki/POWER10#I/O

10ns DDR4 RAM latency, external off-chip memory controller, up to 1 TB/s per socket...whoosh.

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Srdja

[smatovic]

"Intel to Launch Next-Gen Sapphire Rapids Xeon with High Bandwidth Memory"

https://www.anandtech.com/show/16795/in ... dth-memory

...vendors cross-connect already the memory between several GPUs, wonder if we will some kind of memory-centric design in future.

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Srdja

[smatovic]

[...]
...vendors cross-connect already the memory between several GPUs, wonder if we will some kind of memory-centric design in future.
[...]

We can look at the Apple M1 as an kind of memory centric design already, CPU and GPU use 4x128 bit DDR4 memory channels with unified adress space for RAM, dunno about the neural network engine.

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Srdja

[dangi12012]

What wonderful news. And since CPUs and GPUs both can talk to the same greased-lightning fast memory, think of the stories we could tell.

This could be transformative for chessprogramming. Evaluating the board takes the most cpu time. If this can be offloaded to a gpu without a latency impact it will be a wonderful time for us programmers.