AVX-Reference

[Gerd Isenberg]

Sixteen 256-bit registers - but no PPERM instruction as proposed by AMD's SSE5 to permutate bytes combined with various operations like inverse and reverse ;-(
http://softwarecommunity.intel.com/isn/ ... 943302.pdf

If I compare

• 8080 - 6502
  8086 - 68000
  SSE - AltiVec
  AVX - SSE5

... the most ugly instruction set seem to have the greatest success. Why is that?

[Nid Hogge]

Gerd,

Looks like you share the same opinion with many others. http://realworldtech.com/forums/index.c ... 6&roomid=2

Most users tend to agree, But think FMA is a pretty good addition.

Ironcally, it will probably be more widely used than SSE5 regardless of the advantages it might have.

[CRoberson]

MS DOS was vastly inferior to its main competitor. There are numerous
examples where the worst product won.

Seems that people with the worst product try harder at nontechnical
means of winning.

Mr. K. said "..let the public decide..", so IBM sold MS DOS for $50 and his
OS for $500. Given the price for a computer at the time was > $2k,
the unknowing public went for the $50 option. Thus, starting the Bill
Gates empire. Was he better at sales, marketing or kissing IBM's
.... ?

Now, who can name Mr. K and his OS?

[Gerd Isenberg]

Gerd,

Looks like you share the same opinion with many others. http://realworldtech.com/forums/index.c ... 6&roomid=2

Most users tend to agree, But think FMA is a pretty good addition.

Ironcally, it will probably be more widely used than SSE5 regardless of the advantages it might have.

Yes, I found SSE5 much more stringent and versatile for a lot of applications. I hoped Intel would have adapted some of the SSE5 aka AltiVec ideas.

I will pragmatically go with AVX, likely as a 256-bit SSE2 extension. For the standard kogge-stone stuff with vectors of four bitboards this is fine and takes about 2/3 of instructions. But possible application of general hyperbola quintessence relying on bit-reversal of bitboards is not efficiently possible with AVX - or due to byte-shuffling only with diagonal- or file-attacks.

Gerd

[Gerd Isenberg]

Now, who can name Mr. K and his OS?

No idea who Mr. K is. Was it OS/2?

For some (professional) reason I always focused on the Intel/M$ "main-stream", from 8080, 8085, 8086, 8089, 80186, 80286, 80386 was quite fine and so on - and M$-Osses. I think generations of programmers were inveigled

Gerd

[CThinker]

Now, who can name Mr. K and his OS?

No idea who Mr. K is. Was it OS/2?

For some (professional) reason I always focused on the Intel/M$ "main-stream", from 8080, 8085, 8086, 8089, 80186, 80286, 80386 was quite fine and so on - and M$-Osses. I think generations of programmers were inveigled

Gerd

Gary K, and CP/?

[CRoberson]

Dr. Gary Kildall's operating system called CP/M

[Nid Hogge]

Intel's upcoming AVX instructions go back to the future

This past IDF, Intel announced its next major X86 instruction set facelift - the Advanced Vector Extensions, or AVX. What's the big deal, you may ask? After all, there were countless MMX and SSE rounds till this day.

Well, it is a nice 3-operand, RISC-like approach, so you can finally do A+B=C in a single opcode: AMD's proposed SSE5 is supposed to go along this line as well. Later, with fused multiply-adds, this could even become A*B+C=D. Then, you got a more efficient instruction format with a lot of baggage (and length) reduced - again, one of major problems of X86 on efficient fixed-opcode length RISCs. No need to mention the good ship Itanic here, it can have more instruction FORMATS than some RISCs have instructions - that's how 'elegant' it is.

Then, AVX doubles the SSE register length to 256 bits - doubling the amount of data fitting in and, matched with doubled data paths, providing twice the FP throughput per clock in the Sandy Bridge CPU some two years from now. And, one day maybe, you could fit two quad-precision 128-bit FP numbers into each of these registers. Marvellous!

But then, these innovations aren't that new? From the turn of the century, there was something called EV9 - a 2146 4 Alpha CPU somewhere in 2005. The thing was proposed to have one (possibly two) 8-way superscalar EV8 cores, each multithreaded of course. And a dedicated vector engine with 16 MB L3 cache. Now, that was to be an interesting beast for a general-purpose CPU: a 1024-bit wide monster, with matching L3 cache width, and 32 1024-bit wide vector registers (yeah, four kilobytes of numbers in there).

The thing would have achieved 16 parallel 64-bit DP FP mul-adds per clock then, and the humongous register space coupled with ultrawide cache and 16 RDRAM channels would have ensured quite a high practical performance rate, too, something on the order of 100++ DP GFLOPs per core.

Too bad we all know what happend to the Alpha..

http://www.theinquirer.net/gb/inquirer/ ... structions

[bob]

Sixteen 256-bit registers - but no PPERM instruction as proposed by AMD's SSE5 to permutate bytes combined with various operations like inverse and reverse ;-(
http://softwarecommunity.intel.com/isn/ ... 943302.pdf

If I compare

• 8080 - 6502
  8086 - 68000
  SSE - AltiVec
  AVX - SSE5

... the most ugly instruction set seem to have the greatest success. Why is that?

"intel"...