"Correct" benchmarks of modern CPUs for chess

[bob]

One issue is the 4-level virtual-to-real addressing tables AMD uses. A single memory access that results in a TLB miss turns into 5 memory accesses, 4 for the page tables, then one to actually fetch the data. You are probably measuring some of the latter depending on what memory test you used and how much memory you actually requested for the test run.

Allocating 250M shared memory and then reading it randomly from 4 threads in parallel (=hash table access in a chessprogram). I don't think the 4 level tables are enabled by default in Windows?

If this is AMD you have no choice. You can use large pages to get rid of one of the 4 levels, but that's it...