Some Notes about Hyper-Threading

[Daniel Shawul]

HT technology only duplicates the instruction pointer, so there can be two instruction streams, and then alternatingly feeds micro-Opts from one or the other into the execution pipeline. Because instructions from the different streams never have dependencies, out-of-order execution is more effective than on a single stream: if there are no execution-ripe instructions for one stream in the re-order buffer, the execution units will simply work on instructions from the other stream. (There are no extra exeution units, and this part of the CPU is not aware of the HT at all.)

Isn't HT technology using superscalar (out-of-order) computing on two threads _simultaneously_? I think this requires multiple ALU,FPU,bitshifter which most cpus have nowadays. The regular type of interleaved multi threading ,as you described it, context switches between threads to utilize cpu more. But I think HT is a bit different than this since this one can execute two instructions at the same clock using duplicated execution units. But everything else is shared including the L1 cache, so it can give better or worse performance depending on how the program is affected by cache. I think it should generally perform better for many applications, but unfortunately for chess executing more threads adds overhead.

[hgm]

The CPUs have multiple ALUs etc., but in this stage of the pipeline these are not aware which thread they are working for. You are right that the CPU needs to have an extra file of architectuaral registers (EAX etc.), which I forgot to mention. But there are only 8 of those, which is insignificant, as in reality there are already some 100 general registers (the bulk of them organized as a circular 'reorder' buffer) in the CPU. So dedicating 8 more is not a big deal.

The way it works is that each incoming instruction gets assigned the next element of the reorder buffer for its result, and a small 'renaming' register file remembers which physical register that was (and now thus acts as the original architectural destination). The source operands of instructions that arrive later are then remapped according to this renaming file. So the renaming file should be twice as big, and which half is used then depends on the HT the instruction is from.

[Daniel Shawul]

The CPUs have multiple ALUs etc., but in this stage of the pipeline these are not aware which thread they are working for. You are right that the CPU needs to have an extra file of architectuaral registers (EAX etc.), which I forgot to mention. But there are only 8 of those, which is insignificant, as in reality there are already some 100 general registers (the bulk of them organized as a circular 'reorder' buffer) in the CPU. So dedicating 8 more is not a big deal.

The way it works is that each incoming instruction gets assigned the next element of the reorder buffer for its result, and a small 'renaming' register file remembers which physical register that was (and now thus acts as the original architectural destination). The source operands of instructions that arrive later are then remapped according to this renaming file. So the renaming file should be twice as big, and which half is used then depends on the HT the instruction is from.

Thanks. I think what was confusing (and hopefully I now understand) was that HT is associated with superscalar computing. So the duplication of ALU has nothing to do with HT but with superscalar computing which can already work well by re ordering instruction of the same thread. So I was wrong to think that HT by itself needs separate execution units,since it is the superscalar computing that neededed it, and HT just added a thread to add mored 'independence' of instructions. However if HT is used on non-superscalar processor then it can not improve performance well if at all(probably well below 30%). So HT only requires duplication of the resources ( registers etc) besides the existing duplicated units.

[Suj]

Bob,
>I no longer disable HT, I just make sure to use 1 thread per physical core and >let the O/S (Linux in my case) make certain that each physical thread runs on >its own physical core...

Can you elaborate a bit more?

Are you meaning you are setting affinity for crafty to use physical cores?

Just to go slightly off topic: Can the HT cores be used to manage cluster overheads?
Have you done any tests using HT for clusters?

[Suj]

Sedat,

Contact Kevin aka Cummourchess-he is very knowledgeable in this domain as he ran tests for over 2 years on allocating physical cores to processes while using rybka.

Just a hint -try setting affinity to only the even ones-0,2,4,6,8.

There was already a discussion about this 2-3 years back with Kevin,Lucas all contributing to these tests. I can also confirm it was marginally better performance using even cores though power consumption was much more.

What might be interesting is can these HT cores contribute or made to contribute towards cluster overheads? If so how?

[Kingghidorah]

And here's my problem: I tried to disable HT but I didn't find any option in BIOS-Advanced. There's only an utility, "Easy Flash", and I should only use it to browse and find the BIOS file.... but I've no idea about where to search for it.

It's an Asus laptop, X53S series. Any guess?

Thanks in advance.

http://support.asus.com/download/ModelL ... 53S&type=1

Does any of these BIOS upgrades give you access to Hyperthreading tweaking? If they do not then do not fool with BIOS upgrade. A mistake upgrading BIOS can fry your BIOS chip. The "Easy Flash" is the utility that gives you opportunity to change your BIOS. Look and see what your particular BIOS will do for your EXACT model number.

[Vinvin]

Hi Sedat, I've access to an HT machine since few weeks and I noticed windows move 1 thread accross cores. Example : on 4 cores HT, 3 threads is better than 4 ...
So would you mind to test 9 and 10 threads with HT ON ? It could be better (time to depth) than 6 cores with HT OFF ...

Thanks,
Vincent.

Hello Vincent,

Interesting...

Right now my i7 980X/i7 970 machines are busy...
But later i will try to test 9,10 and 11 threads with HT ON

Best,
Sedat

After some observation, threads seems stay in same core. May be test only with 9 threads, if it's not positive, there's probably nothing to find there ...