Intel says its next-gen chips will be optimized for neural networks

[jdart]

https://www.zdnet.com/article/intel-arc ... processor/

Koduri claimed that by speeding up the matrix multiplications at the heart of neural networks, Intel will have the fastest chips for machine learning and deep learning, and any form of artificial intelligence processing.

He is talking about both CPUs and GPUs. Of course, we will see better once they're out there and benchmarked.

[Sopel]

The cpus will have avx_vnni and will be able to do 3 256-bit loads per cycle. If these instructions don't throttle it will be a big win for NNUE.

[smatovic]

The cpus will have avx_vnni and will be able to do 3 256-bit loads per cycle. If these instructions don't throttle it will be a big win for NNUE.

The new thingy with Xeon Sapphire Rapids is going to be the AMX, advanced matrix multiplication, stuff, maybe someday SF will switch from MLP to CNN design?

https://talkchess.com/forum3/viewtopic. ... 7&p=850363

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Srdja

[ChickenLogic]

Alder Lake consumer chips will be completely cut off from AVX512. It is very likely that Zen4 will come with some kind of AVX-512 support. We'll see how it goes. Also, V-Cache tech from AMD will add 64 MB of L3 cache per CCX. This will also be huge for NNUE. The future for CPUs look bright ever since AMD picked up pace.
It remains to be seen how well Intel's new CPUs will perform under heavy AVX-512 workloads. For now it's pretty hit and miss whether it gains a lot or slows SF down.

[Milos]

The cpus will have avx_vnni and will be able to do 3 256-bit loads per cycle. If these instructions don't throttle it will be a big win for NNUE.

The new thingy with Xeon Sapphire Rapids is going to be the AMX, advanced matrix multiplication, stuff, maybe someday SF will switch from MLP to CNN design?

https://talkchess.com/forum3/viewtopic. ... 7&p=850363

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Srdja

With 10nm node they can achieve atm, I doubt they'll be competitive in any way to NVIDIA GPUs. There is not much to invent when matrix multiplication implementation is in question. So the main thing that makes the difference in performance is the process node. And TSMC (and even Samsung) 5nm is just killing Intel's 10nm.

[jdart]

Alder Lake consumer chips will be completely cut off from AVX512

Yep, it looks like AVX512 and AMX will be only in the server chips, the "Xeon Scalable" series. Those will also have nice high core counts, but probably multi-thousand dollar prices at the high end. I don't even see an indication that you'll get workstation type chips with those instructions, just the multi-socket Xeons, which have always been very pricey.

[Sopel]

The cpus will have avx_vnni and will be able to do 3 256-bit loads per cycle. If these instructions don't throttle it will be a big win for NNUE.

The new thingy with Xeon Sapphire Rapids is going to be the AMX, advanced matrix multiplication, stuff, maybe someday SF will switch from MLP to CNN design?

https://talkchess.com/forum3/viewtopic. ... 7&p=850363

--
Srdja

With 10nm node they can achieve atm, I doubt they'll be competitive in any way to NVIDIA GPUs. There is not much to invent when matrix multiplication implementation is in question. So the main thing that makes the difference in performance is the process node. And TSMC (and even Samsung) 5nm is just killing Intel's 10nm.

This will obviously not compete with GPUs, this is for low-latency applications, like NNUE for example.

[ChickenLogic]

AVX512 has the problem of being a gamble that the CPU will stay cool enough/not clock down too much as of now (at least with Intel processors). If AMD gets it right I suspect lot's more applications will start to adopt it. Linear algebra is really useful.